|
5 J+ u4 n& d! Y) f7 \. s4 F: S" z& Y6 L
寄存器初始化那里就给出来了啊,如果DSP要发数据给FPGA, 那么CLOCK是由DSP去控制的,如果DSP要接收FPGA的数据,则CLOCK是由FPGA控制的,START跟ENABLE信号是用来控制发送使能的。这是我的初始化配置(我是用8位宽度通信的,对于DSP来说,B是发送,A是接收):
+ k+ J$ f* n, s3 a) B, a% xstatic void UPPInit(void)/ A8 u( n* U: g3 g2 h) V1 z* K
{8 N4 C: X5 D( E- Y S( F
unsigned int temp_reg = 0;. g' v! e: A* C8 x
* K+ A- w b8 k: r& L1 `4 [# V" k
// Channel B params
' T* Z9 f2 m$ Z% J) f7 N CSL_FINST(temp_reg, UPP_UPCTL_DPFB, LJZF); //Left-justified, zero filled2 j& ?8 G# R5 q9 ]/ J$ I4 y. A6 I
CSL_FINST(temp_reg, UPP_UPCTL_IWB, 8BIT); //8-bit interface
- ?; E% p/ s8 N7 O; f; y9 t CSL_FINST(temp_reg, UPP_UPCTL_DPWB, FULL); //Channel B bit width = 8' e& \; C# E; x$ z+ u5 G
CSL_FINST(temp_reg, UPP_UPCTL_DRB, SINGLE); //Single data rate
+ U& C+ j6 H' N3 s2 S; |0 E! b" z$ i( Q n" y
// Channel A params
: `/ a5 d: Z* A l. H CSL_FINST(temp_reg, UPP_UPCTL_DPFA, LJZF); //Left-justified, zero filled
A F1 g l8 ` CSL_FINST(temp_reg, UPP_UPCTL_IWA, 8BIT); //8-bit interface7 V% J" l: K; ~8 r) q v- _) i
CSL_FINST(temp_reg, UPP_UPCTL_DPWA, FULL); //Channel A bit width = 8
$ Z" T$ }( c7 J2 W% @ CSL_FINST(temp_reg, UPP_UPCTL_DRA, SINGLE); //Single data rate6 ^' W9 o" e9 ?$ N
7 J" h3 `* Y* B$ O
CSL_FINST(temp_reg, UPP_UPCTL_CHN, TWO); //Channel A and Channel B are both active.6 W/ A6 Y% [' H
CSL_FINST(temp_reg, UPP_UPCTL_MODE, DUPLEX0); //Channel B transmit Channel A receive
' N# T$ _$ C H$ W5 k6 F- k/ U5 Y6 O9 [
upp_reg_hdl->UPCTL = temp_reg;
! p$ g0 E9 ]9 n4 |, {, V$ n' K0 r: _. j Y
temp_reg = 0;
) g$ g; V2 t( @( e
' a' `9 q5 F0 Z$ C% N f' J // Channel A params5 \ t) b3 @. B7 b
//CSL_FINST(temp_reg, UPP_UPICR_TRISA, ENABLE); //Channel A data pins are in a high-impedance state while idle9 ~, O( ?6 D; D) X6 x
//CSL_FINS(temp_reg, UPP_UPICR_CLKDIVA, UPP_CLOCK_DIV); //Clock divisor0 t/ W; V( M: l
CSL_FINST(temp_reg, UPP_UPICR_STARTA, ENABLE); //Channel A START Signal Enable.
3 @; g5 G$ J" s, d CSL_FINST(temp_reg, UPP_UPICR_ENAA, ENABLE); //Channel A ENABLE Signal Enable
6 ?- ~& }( M1 l8 B1 ?. ?7 |6 Z
% N6 h _/ r5 Y9 ? // Channel B params
, h* A( |1 p6 O4 H CSL_FINS(temp_reg, UPP_UPICR_CLKDIVB, UPP_CLOCK_DIV);
; f2 y% Q: f) U3 t CSL_FINST(temp_reg, UPP_UPICR_STARTB, ENABLE); //Channel B START Signal Enable.) o8 M; [+ ~+ c. W! k1 p2 \
CSL_FINST(temp_reg, UPP_UPICR_ENAB, ENABLE); //Channel B ENABLE Signal Enable
$ W/ X: p0 T/ \% `) `' R0 g' _" C) m7 X! Z1 L+ g9 t# Z
upp_reg_hdl->UPICR = temp_reg;
# Y7 x8 P. Y6 o, X4 c% P p
$ P* y6 T! S# b5 R //temp_reg = 0;
3 \2 x6 `4 b, L8 v" d" `, B6 V A2 [( y& f! I
//CSL_FINS(temp_reg, UPP_UPIVR_VALB, 0x7b7b); //Channel B idle value
0 w+ m9 Y0 g( t3 G1 g //CSL_FINS(temp_reg, UPP_UPIVR_VALA, 0x7f7f); //Channel A idle value$ E5 V: H8 _2 \/ ~2 G
. g! O! N. a4 y! J //upp_reg_hdl->UPIVR = temp_reg;
Y7 j/ V0 k* l! Z
( ~4 c5 A. C: d //temp_reg = 0;8 v' d8 @- W/ u' l6 u0 J
; S, g% b7 E) C# J //CSL_FINST(temp_reg, UPP_UPTCR_RDSIZEI, 256B); //set 256B DMA I , \9 P; M; u9 O9 a& u
//upp_reg_hdl->UPTCR = temp_reg;) r5 I! B0 _1 E- H6 q
5 `' @) t9 q% L$ O2 w //temp_reg = 0;
1 ~* _$ n4 v. M2 w //CSL_FINST(temp_reg, UPP_UPDLB_BA, ENABLE); //B to A loopback mode enable! `: y; d' L3 ]* w
//upp_reg_hdl->UPDLB = temp_reg;4 O7 C" a& s5 _2 Y( b
4 x+ B" i6 E* Z O" f w} |
|