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寄存器初始化那里就给出来了啊,如果DSP要发数据给FPGA, 那么CLOCK是由DSP去控制的,如果DSP要接收FPGA的数据,则CLOCK是由FPGA控制的,START跟ENABLE信号是用来控制发送使能的。这是我的初始化配置(我是用8位宽度通信的,对于DSP来说,B是发送,A是接收):0 I% h* \5 q% e8 l% x. v
static void UPPInit(void)( G/ L' l. m: Z0 {( Y
{
6 v' k8 W. `& N! L8 } unsigned int temp_reg = 0;
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// Channel B params* t, d3 ~' H; T. |% p1 a4 _2 {/ A- d
CSL_FINST(temp_reg, UPP_UPCTL_DPFB, LJZF); //Left-justified, zero filled& w+ r* r6 K) q7 _$ t6 t6 r( J
CSL_FINST(temp_reg, UPP_UPCTL_IWB, 8BIT); //8-bit interface C& e5 S( Q" v& t& K$ T+ F! {
CSL_FINST(temp_reg, UPP_UPCTL_DPWB, FULL); //Channel B bit width = 8
( h7 r5 W, u8 V; ^4 u CSL_FINST(temp_reg, UPP_UPCTL_DRB, SINGLE); //Single data rate* S" s5 z; C3 r. ]) h% X1 s
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// Channel A params/ K( q) R' j4 u- U! W! @2 A
CSL_FINST(temp_reg, UPP_UPCTL_DPFA, LJZF); //Left-justified, zero filled
, G, [5 j: @9 Z( }* v7 H f8 s* b CSL_FINST(temp_reg, UPP_UPCTL_IWA, 8BIT); //8-bit interface8 M% ]: V. I# P5 |5 a2 J2 T2 |
CSL_FINST(temp_reg, UPP_UPCTL_DPWA, FULL); //Channel A bit width = 8
4 E p6 m% o0 O+ o CSL_FINST(temp_reg, UPP_UPCTL_DRA, SINGLE); //Single data rate
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CSL_FINST(temp_reg, UPP_UPCTL_CHN, TWO); //Channel A and Channel B are both active.
+ V% w1 @9 V6 y& i CSL_FINST(temp_reg, UPP_UPCTL_MODE, DUPLEX0); //Channel B transmit Channel A receive* \0 X# G# G" z7 S9 a+ ]7 X! x
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upp_reg_hdl->UPCTL = temp_reg;: [0 Y* |6 A9 G' ~
) k F8 c L' p9 G temp_reg = 0;
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// Channel A params8 U5 C: `9 ]7 ~0 X" N
//CSL_FINST(temp_reg, UPP_UPICR_TRISA, ENABLE); //Channel A data pins are in a high-impedance state while idle
: D. Z# g$ h! x8 g* d //CSL_FINS(temp_reg, UPP_UPICR_CLKDIVA, UPP_CLOCK_DIV); //Clock divisor; K( `0 |8 t" ?/ s: `
CSL_FINST(temp_reg, UPP_UPICR_STARTA, ENABLE); //Channel A START Signal Enable.% G% i; X! s, o4 L
CSL_FINST(temp_reg, UPP_UPICR_ENAA, ENABLE); //Channel A ENABLE Signal Enable4 N. S2 H' j8 g6 H+ ~" `
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// Channel B params4 s; T! B) Z p0 e; P! E) C
CSL_FINS(temp_reg, UPP_UPICR_CLKDIVB, UPP_CLOCK_DIV);# v# @+ l1 M0 \4 c4 F, E
CSL_FINST(temp_reg, UPP_UPICR_STARTB, ENABLE); //Channel B START Signal Enable.5 P9 @% K( C, w
CSL_FINST(temp_reg, UPP_UPICR_ENAB, ENABLE); //Channel B ENABLE Signal Enable
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0 E+ }) U1 z6 ?* @: b9 q upp_reg_hdl->UPICR = temp_reg;% d: r: q" p) J" }9 T( f% l
0 a3 p/ e" S0 P4 t) v' y //temp_reg = 0;# c: {3 l+ {$ s7 o% x& q
# H; Q) z2 @/ ^. n8 L) e //CSL_FINS(temp_reg, UPP_UPIVR_VALB, 0x7b7b); //Channel B idle value* A. d7 N7 \! ~; X; G
//CSL_FINS(temp_reg, UPP_UPIVR_VALA, 0x7f7f); //Channel A idle value3 j4 ^0 l' W- E; b
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//upp_reg_hdl->UPIVR = temp_reg; S( n1 B. S- d) u7 y$ [' B5 v
. G/ i# p. f$ Y: c //temp_reg = 0;
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//CSL_FINST(temp_reg, UPP_UPTCR_RDSIZEI, 256B); //set 256B DMA I 0 v0 O9 l u- i$ e3 k
//upp_reg_hdl->UPTCR = temp_reg;$ T0 O# n8 C7 J+ ]( i) ?6 u$ U
7 U7 x' z; C8 n1 W( s% @+ k/ \ //temp_reg = 0;
% W& d9 _' b7 R2 Y& z //CSL_FINST(temp_reg, UPP_UPDLB_BA, ENABLE); //B to A loopback mode enable
1 U: y: b! {7 U9 S+ d% ] //upp_reg_hdl->UPDLB = temp_reg;9 ^. C/ v _" x% h2 x6 i
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